The verification of the hardware implementation of packet classification algorithm on multiple fields by Veriolg-HDL

Verilog-HDL을 이용한 다중필드 패킷분류 알고리듬의 설계 검증

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.