Design of a Full-Adder Using Current-Mode Multiple-Valued Logic CMOS Circuits

전류 모드 CMOS 다치 논리 회로를 이용한 전가산기 설계

This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.