Preventing a Gate Oxide Thinning in C-MOS process Using a Dual Gate Oxide

Dual Gate Oxide 공정에서 Gate Oxide Thinning 방지에 대한 고찰

  • 김성환 (삼성전자 SYSTEM LSI사업부) ;
  • 김재욱 (고려대학교 전기공학과) ;
  • 성만영 (고려대학교 전기공학과)
  • Published : 2003.07.10

Abstract

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.

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