A new driving circuit for the low power and reduced layout area in silicon based AM-OELDs

  • Lee, Cheon-An (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Yoon, Yong-Jin (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Jin, Sung-Hun (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Kim, Jin-Wook (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Kwon, Hyuck-In (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Lee, Jong-Duk (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University) ;
  • Park, Byung-Gook (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University)
  • Published : 2003.07.09

Abstract

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.

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