High Current Stress characteristics on Sequential Lateral Solidification (SLS) Poly-Si TFT

  • Jung, Kwan-Wook (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Kim, Ung-Sik (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Kang, Myoung-Ku (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Choi, Pil-Mo (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Lee, Su-Kyeong (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Kim, Hyun-Jae (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Kim, Chi-Woo (LCD R&D center AMLCD division Samsung Electronics.) ;
  • Jung, Kyu-Ha (LCD R&D center AMLCD division Samsung Electronics.)
  • 발행 : 2003.07.09

초록

The reliability of TFT, crystallized by sequential lateral solidification (SLS) technology, has been studied High current damage is characterized by high gate bias (-20V) and drain bias (-10V). It is found that performance of SLS TFTs is enhanced by high current stress up to 300 sec of stress time for 20/8 (W/L) N-TFT. After that, TFT performance is degraded with the increase of the stress time. It is speculated from the experimental data that SLS TFTs initially contain a number of unstable defect states. Then, the defect states seem to be cured by high current stress.

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