Measurement of Wall Voltage in Reset Discharge of AC PDP

In AC plasma display, it is very important to quantify the wall voltage induced by the wall charge accumulated on the dielectric surface. If we know the quantities of the wall voltage in each period of every sequence; reset period, address period and sustain period, then it helps us to design the optimal driving waveform for high efficiency plasma display. We develop a new method to measure the wall voltage with VDS (Versatile Driving Simulator) system. From this method the wall voltage induced by a wall charge profiles just after the reset discharge of every cells in plasma display panel can be investigated and analyzed successfully. It is noted that the wall voltage profiles are influenced by the space charge and then they are stabilized as time goes by. It is also noted that both the remaining wall charge at the previous sequence and space charges contribute to wall voltage quantities just after the reset discharge. It is noted that the wall charges contribute dominantly after a few hundreds microseconds, while the space charges have been decayed within 100 ${\mu}s$ just after the reset discharge.