Development of New LTPS Process

We have developed the five mask $PMOS^1$ and the six mask CMOS process architecture for poly-Si TFT. In order to have a competitive process with that for a-Si TFT, the simple co-planar electrode structure whose data line electrode and pixel electrode are on the same plane was adopted. In addition, RGB + White four color $technology^2$ were applied to achieve high aperture ratio and transmittance. Using the aforementioned process architecture and four color technology, 2.0 inch qCIF transmissive micro-reflectance (TMR) device was successfully fabricated.