Low-Swing CVSL 전가산기를 이용한 저 전력 8$\times$8 비트 병렬 곱셈기 설계

Design of a Low-Power 8$\times$8 bit Parallel Multiplier Using Low-Swing CVSL Full Adder

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.