Microcrystalline Si TFTs with Low Off-Current and High Reliability

Microcrystalline Si (${\mu}c-Si$) TFTs were fabricated using a conventional bottom gate amorphous Si (a-Si) process. A unique ${\mu}c-Si$ deposition technique and TFT architecture was proposed to enhance the reliability of the TFTs. This three-mask TFT fabrication process is comparable with existing a-Si TFT procesess. In order to suppress nucleation at the bottom interface of Si, before deposition of the ${\mu}c-Si$ an $N_2$ plasma passivation was conducted. A typical transfer characteristic of the TFTs shows a low off-current with a value of less than 1 pA and a sub threshold slop of 0.7 V/dec. The DC stress was applied to verify the use of ${\mu}c-Si$ TFTs for AMOLED displays. After 10,000 s of application of the stress, the off-current was even lowered and sub-threshold slope variation was less than 5%. For AMOLED displays, OLED pixel simulation was performed. A pixel current of 13 ${\mu}A$ was achieved with $V_{data}$ of 10 V. After the simulation, a linear equation for the pixel current was suggested.