LAYOUT VERIFICATION METHOD FOR DESIGNING AND MANUFACTURING OF LCOS/AM OLED MICRODISPLAY BACKPLANES

  • Smirnov, A.G. (Belarusian State University of Informatics and Radioelectronics (BSUIR)) ;
  • Koukharenko, S.N. (Belarusian State University of Informatics and Radioelectronics (BSUIR)) ;
  • Volk, S.V. (Belarusian State University of Informatics and Radioelectronics (BSUIR)) ;
  • Zayats, A.M. (Belarusian State University of Informatics and Radioelectronics (BSUIR))
  • Published : 2006.08.22

Abstract

In this presentation we will describe two core elements, which combination gives a new approach to layout verification; they are a computational algorithm for modeling of photolithographical processes and a method for physical layout verification that uses output contours of that algorithm. Utilization of this approach allows to improve the quality of LCOS/AM OLED backplanes physical verification, because it considers discrepancies between mask features and printed contours on a wafer.

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