한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)

한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
권호 표지

비소 고상확산방법을 이용한 MOSFET SOI FinFET 소자 제작

Fabrication of SOI FinFET devices using Aresnic solid-phase-diffusion

  • 조원주 (광운대학교 전자재료공학과) ;
  • 구현모 (광운대학교 전자재료공학과) ;
  • 이우현 (광운대학교 전자재료공학과) ;
  • 구상모 (광운대학교 전자재료공학과) ;
  • 정홍배 (광운대학교 전자재료공학과)
  • Cho, Won-Ju (Department of Electronic materials engineering Kwangwoon Univ.) ;
  • Koo, Hyun-Mo (Department of Electronic materials engineering Kwangwoon Univ.) ;
  • Lee, Woo-Hyun (Department of Electronic materials engineering Kwangwoon Univ.) ;
  • Koo, Sang-Mo (Department of Electronic materials engineering Kwangwoon Univ.) ;
  • Chung, Hong-Bay (Department of Electronic materials engineering Kwangwoon Univ.)
  • 발행 : 2006.11.09
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초록

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

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