Evaluation of nano-sSOI wafer using pseudo-MOSFET

Pseudo-MOSFET을 이용한 nano-sSOI 기판의 특성 평가

  • Jung, Myung-Ho (Department of Electronic materials engineering, Kwangwon Univ.) ;
  • Kim, Kwan-Su (Department of Electronic materials engineering, Kwangwon Univ.) ;
  • Choi, Chel-Jong (Nano-Bio Electronic Devices Team, Electronics and Telecommunications Research Institute) ;
  • Cho, Won-Ju (Department of Electronic materials engineering, Kwangwon Univ.)
  • 정명호 (광운대학교 전자재료공학과) ;
  • 김관수 (광운대학교 전자재료공학과) ;
  • 최철종 (한국전자통신연구원 IT 융합 부품 연구소) ;
  • 조원주 (광운대학교 전자재료공학과)
  • Published : 2007.11.01

Abstract

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

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