Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Low Power SAD Processor Architecture for Motion Estimation of K264

K264 Motion Estimation용 저전력 SAD 프로세서 설계

  • Kim, Bee-Chul (School of Computer, Information and Communication Engineering Sangmyung University) ;
  • Oh, Se-Man (School of Computer, Information and Communication Engineering Sangmyung University) ;
  • Yoo, Hyeon-Joong (School of Computer, Information and Communication Engineering Sangmyung University) ;
  • Jang, Young-Beom (School of Computer, Information and Communication Engineering Sangmyung University)
  • 김비철 (상명대학교 컴퓨터정보통신 공학과) ;
  • 오세만 (상명대학교 컴퓨터정보통신 공학과) ;
  • 유현중 (상명대학교 컴퓨터정보통신 공학과) ;
  • 장영범 (상명대학교 컴퓨터정보통신 공학과)
  • Published : 2007.07.11
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

Keywords