Timing violation의 효율적인 수정을 위한 closure 방법의 제안

A New Closure Method for Efficient Modification of Timing Violation

In this paper, we propose an efficient timing closure methodology during physical implementation. Many types of slacks and closure solutions were introduced case-by-case. The major part of violations was managed by specified tools, but the exceptionally generated minor violation which was occurred through correlation error between tools was manually corrected by ASIC engineer. From the proposed method, we identified that the best effective method is to decrease the sum of intrinsic delay in case of setup time violation.