Simulation of Junction Field Effect Transistor using SiGe-Si-SiGe Channel Structure

SiGe-Si-SiGe 채널구조를 이용한 JFET 시뮬레이션

  • Park, B.G. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
  • Yang, H.Y. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
  • Kim, T.S. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
  • Shim, K.H. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University)
  • 박병관 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
  • 양하용 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
  • 김택성 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
  • 심규환 (전북대학교 반도체.화학공학부 반도체 물성연구소)
  • Published : 2008.11.06

Abstract

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

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