Threshold voltage control in dual gate ZnO-based thin film transistors

  • Park, Chan-Ho (Institute of Physics and Applied Physics, Yonsei University) ;
  • Lee, Ki-Moon (Institute of Physics and Applied Physics, Yonsei University) ;
  • Lee, Kwang-H. (Institute of Physics and Applied Physics, Yonsei University) ;
  • Lee, Byoung-H. (Department of Chemistry, Hanyang University) ;
  • Sung, Myung-M. (Department of Chemistry, Hanyang University) ;
  • Im, Seong-Il (Institute of Physics and Applied Physics, Yonsei University)
  • 발행 : 2009.10.12

초록

We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20 nm-thick $Al_2O_3$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at $200^{\circ}C$. Whether top or bottom gate is biased for sweep, our TFT almost symmetrically operates under a low voltage of 5 V showing a field mobility of ~0.4 $cm^2/V{\cdot}s$ along with the on/off ratio of $5{\times}10^4$. The threshold voltage of our DG TFT was systematically controlled from 0.5 to 2.0 V by varying counter gate input from +5 to -2 V.

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