A Capacitorless 1-Transistor DRAM Device using Strained-Silicon-on-Insulator (sSOI) Substrate

Strained-Silicon-on-Insulator (sSOI) 기판을 이용한 Capacitorless 1-Transistor DRAM 소자

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.