Ion beam etching of sub-30nm scale Magnetic Tunnel Junction for minimizing sidewall leakage path

  • Kim, Dae-Hong (Department of Electronic Engineering, Hanyang University) ;
  • Kim, Bong-Ho (Department of Electronic Engineering, Hanyang University) ;
  • Chun, Sung-Woo (Department of Electronic Engineering, Hanyang University) ;
  • Kwon, Ji-Hun (Department of Electronic Engineering, Hanyang University) ;
  • Choi, Seon-Jun (Department of Electronic Engineering, Hanyang University) ;
  • Lee, Seung-Beck (Department of Electronic Engineering, Hanyang University)
  • Published : 2011.12.05

Abstract

We have demonstrated the fabrication of sub 30 nm MTJ pillars with PMA characteristics. The multi-step IBE process performed at $45^{\circ}$ and $30^{\circ}$, using NER resulted in almost vertical side profiles. There deposition on the sidewalls of the NER prevented lateral etching of the resist hard mask allowing vertical MTJ side profile formation without any reduction in the lithographically defined resist lateral dimensions. For the 28nm STT-MTJ pillars, the measured TMR ratio was 13 % with resistance of 1 $k{\Omega}$, which was due to remaining redeposition layers less than 0.1 nm thick. With further optimization in multi-step IBE conditions, it will be possible to fabricate fully operating sub 30 nm perpendicular STT-MTJ structures for application to future non-volatile memories.

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