Proceeding of EDISON Challenge (EDISON SW 활용 경진대회 논문집)

Korea Institute of Science and Technology Information (한국과학기술정보연구원)
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Optimum Channel Thickness of Nanowire-FET

  • Go, Hyeong-U (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Jong-Su (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Sin-Geun (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Sin, Hyeong-Cheol (Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University)
  • Published : 2016.03.22
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Abstract

Nanowire-FET은 Gate-All-Around (GAA) 구조로 차세대 반도체 소자 구조로 여겨지고 있다. Nanowire-FET은 채널 두께에 따라 $I_D-V_G$ curve에 매우 중요한 영향을 끼친다. 따라서 본 논문은, Edison 시뮬레이션을 이용하여 Nanowire-FET의 Silicon Thickness에 따른 여러 특성을 비교하여 최적 Silicon Thickness에 대해 연구하였다.

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