Multiple Fault Detection in Combinational Logic Networks

조합논리회로의 다중결함검출

In this paper, a procedure for deriving of multiple fault detection test sets is presented for fan-out reconvergent combinational logic networks. A fan-out network is decomposed into a set of fan-out free subnetworks by breaking the internal fan-out points, and the minimal detecting test sets for each subnetwork are found separately. And then, the compatible tests amonng each test set are combined maximally into composite tests to generate primary input binary vectors. The technique for generating minimal test experiments which cover all the possible faults is illustrated in detail by examples.

본 논문에서는 분기가 있는 일반조합논리회로의 다중결함을 검출할 수 있는 테스트집합을 구하는 절차를 유도하였다. 일반논리회로를 우선 내부분기점을 전후하여 이를 분기가 없는 부분회로로 분리하고 각 부분회로에 대한 최소테스트집합을 구한다. 다음에 각 부분테스트를 최대한으로 병립시켜 합성테스트를 구하여 종합적인 일차입력벡터를 정한다. 이러날 수 있는 모든 결함을 빠짐없이 피복할 수 있는 최소테스트집합을 구해가는 과정에 대해서는 각 를 들어 상세히 설명하였다. In this paper, a procedure for deriving of multiple fault detection test sets is presented for fan-out reconvergent combinational logic networks. A fan-out network is decomposed into a set of fan-out free subnetworks by breaking the internal fan-out points, and the minimal detecting test sets for each subnetwork are found separately. And then, the compatible tests amonng each test set are combined maximally into composite tests to generate primary input binary vectors. The technique for generating minimal test experiments which cover all the possible faults is illustrated in detail by examples.