Output Phase Assignment Algorithm for Multilevel Logic Synthesis

다단 논리합성을 위한 출력 Phase 할당 알고리즘

This paper presents a new output phase assignment algorithm which determines the phases of all the nodes in a given boolean network. An estimation function is defined, which is represented by the relation between the literals in the given function expression. A weight function, WT (fi, fj) is defined, which is represented by approximate amount of common subexpression between function fi and fj. Common Subexpression Graph(CSG) is generated for phase selection by the weight function between all given functions. We propose a heuristic algorithm finding subgraph of which sum of weights has maximum by assigning phases into the given functions. The experiments with MCNC benchmarks show the efficiency of the proposed method.