Effect of Thermal Budget of BPSG flow on the Device Characteristics in Sub-Micron CMOS DRAMs

서브마이크론 CMOS DRAM의 소자 특성에 대한 BPSG Flow 열처리 영향

  • Lee, Sang-Gyu (Semiconductor Research and Development Laboratory, Hyundai Electronics Industries Co.) ;
  • Kim, Jeong-Tae (Semiconductor Research and Development Laboratory, Hyundai Electronics Industries Co.) ;
  • Go, Cheol-Gi (Semiconductor Research and Development Laboratory, Hyundai Electronics Industries Co.)
  • 이상규 (현대전자(주) 반도체 연구소) ;
  • 김정태 (현대전자(주) 반도체 연구소) ;
  • 고철기 (현대전자(주) 반도체 연구소)
  • Published : 1991.10.01

Abstract

A comparision was made on the influence of BPSG flow temperatures on the electrical properties in submicron CMOS DRAMs containing two BPSG layers. Three different combinations of BPSG flow temperature such as $850^{\circ}C/850^{\circ}C,\;850^{\circ}C/900^{\circ}C,\;and\;900^{\circ}C/900^{\circ}C$ were employed and analyzed in terms of threshold, breakdown and isolation voltage along with sheet resistance and contact resistance. In case of $900^{\circ}C/900^{\circ}C$ flow, the threshold voltage of NMOS was decreased rapidly in channel length less than $0.8\mu\textrm{m}$ with no noticeable change in PMOS and a drastic decrease in breakdown voltages of NMOS and PMOS was observed in channel length less than and equal to $0.7\mu\textrm{m}$ and $0.8\mu\textrm{m}$, respectively. Little changes in threshold and breakdown voltages of NMOS and PMOS, however, were shown down to channel length of $0.6\mu\textrm{m}$ in case of $850^{\circ}C/850^{\circ}C$ flow. The isolation voltage was increased with decreasing BPSG flow temperature. A significant increase in the sheet resistance and contact resistance was noticeable with decreasing BPSG flow temperature from $900^{\circ}C$ to $850^{\circ}C$. All these observations were rationalized in terms of dopant diffusion and activation upon BPSG flow temperature. Some suggestions for improving contact resistance were made.

2충의 BPSG를 사용하는 서브마이크론 CMOS DRAM에 있어 전기적 특성에 관한 BPSG flow온도의 영향을 비교하였다. BPSG flow온도를 $850^{\circ}C/850^{\circ}C,\;850^{\circ}C/900^{\circ}C,\;900^{\circ}C/900^{\circ}C$의 3가지 다른 조합을 적용하여 문턱전압, 파괴전압, Isolation전압과 더불어 면저항과 접촉 저항을 조사하였다. $900^{\circ}C/900^{\circ}C$ flow의 경우 NMOS에서 문턱전압은 $0.8\mu\textrm{m}$ 미만의 채널길이에서 급격히 감소하나 PMOS 경우는 차이가 없었다. NMOS와 PMOS의 파괴전압은 각각 $0.7\mu\textrm{m}$$0.8\mu\textrm{m}$ 이하에서 급격히 감소하였다. 그러나 $850^{\circ}C/850^{\circ}C$ flow의 경우에는 NMOS와 PMOS모두 문턱전압과 파괴전압은 채널길이 $0.7\mu\textrm{m}$까지 감소하지 않았다. Isolation전압은 BPSG flow온도 감소에 따라 증가하였다. 면저항과 접촉 저항은 BPSG flow온도가 $900^{\circ}C$에서 $850^{\circ}C$로 감소됨에 따라 급격히 증가되었다. 이와 같은 결과는 열처리 온도에 따라 dopant의 확산과 활성화에 관련 있는 것으로 생각된다. 접촉 저항 증가에 대한 개선 방법에 대하여 고찰하였다.

Keywords

References

  1. J. Vac. Sci. Technol. v.B4 no.3 F. S. Becket;D.Pawlik;H. Schafer;G. Staudgl
  2. The Electrochemical Society Extended Abstracts V. V. S. Rana;A. S. Manocha;E. P. Martin;G. J. Felton;A. S. Harrus;A. K. Shina
  3. J. Electrochem. Soc. v.134 no.11 F. S. Beacker;S. Rohl
  4. 月刊 Semiconductor World v.9 no.10 魚落泰雄
  5. J. Electrochem. Soc. v.134 no.3 D. S. Williams;E. A. Dein
  6. J. Electrochem. Soc. v.134 no.2 R. A. Levy;P. K. Galogher;F. Schrey
  7. J. Electroche,. Soc. v.137 no.9 K. Fujion, Y. Nishimoto, N. Tokumasu;K. Maeda
  8. Silicides for VLSI Applications S. P. Murarka
  9. Polycrystalline Silicon for Integrated Circuit Application Ted Kamins
  10. J. Electrochem. Soc. v.129 no.9 S. Solmi;M. Severi;L. Balchi
  11. VMIC T. Hamajima;Y. Sugano
  12. VMIC Farhad K. Moghadam;Kwang Sub
  13. VMIC J. M. Dryanan;E.Ikawa;T. Kikkawa
  14. VMIC S. Saito;K. Nakamura;K. Matsuda;K. Sakiyama