Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 29A Issue 2
- /
- Pages.88-99
- /
- 1992
- /
- 1016-135X(pISSN)
Design of a Technology Mapping System for Logic Circuits
논리 회로의 기술 매핑 시스템 설계
Abstract
This paper presents an efficient method of mapping Boolean equations to a set of library gates. The proposed system performs technology mapping by graph covering. To select optimal area cover, a new cost function and local area optimization are proposed. Experimental results show that the proposed algorithm produces effective mapping using given library.
Keywords