Design of A Logic/Timing Extraction System for Higher-level Design Verification

상위단계 설계 검증을 위한 논리/타이밍 추출 시스템의 설계

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.