Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The Fabrication of the 0.1$\mu\textrm{m}$ NMOSFET by E-beam Lithography

E-beam lithography를 이용한 0.1$\mu\textrm{m}$ NMOSFET 제작

  • 유상기 (서울대학교 반도체공동연구소) ;
  • 김여환 (서울대학교 반도체공동연구소) ;
  • 전국진 (서울대학교 반도체공동연구소) ;
  • 이종덕 (서울대학교 반도체공동연구소)
  • Published : 1994.01.01
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Abstract

The NMOSFET with gate length of 0.1$\mu$m is fabricated by mix-and-match method. In this device, the electron beam lithography is used to form the gate layer, while other layers are formed by the stepper. The gate oxide is 7nm thick, and the device structure is normal LDD structure. The saturation Gm for gate length of 0.1$\mu$m is 246mS/mm. The subthreshold slope is 180mV/decade for 0.1$\mu$m gate length, but the slope is 80mV/decade for 0.3$\mu$m gate length.

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