New Transistor Sizing Algorithms For CMOS Digital Designs

CMOS 디지틀 설계를 위한 트랜지스터 크기의 최적화기법

  • 이상헌 (한국과학기술원 전기 및 전자공학과) ;
  • 김경호 (삼성전자 반도체부문 연구소 CAE팀) ;
  • 박송배 (한국과학기술원 전기 및 전자공학과)
  • Published : 1994.03.01

Abstract

In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.

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