A Study on Synthesis of VHDL Sequential Statements at Register Transfer Level

레지스터 전송 수준에서의 VHDL 순서문 합성에 관한 연구

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.