전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제31A권6호
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- Pages.128-133
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- 1994
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- 1016-135X(pISSN)
저전력형 TTL-to-CMOS 변환기의 설계
Design of low power TTL-to-CMOS converter
초록
This paper proposes a new TTL-to-CMOS converter which has low power dissipation. This converter has no static power dissipation for typical TTL output voltage levels. The simulatio result shows that the power dissipation is reduced to about 1/20 of conventional level converter using CMOS inverters. It also has hysteresis due to the positive feedback which makes the converter noise immune. The logic threshold voltages in the hysteresis characteristic can be optimized by changing the size ratios of the transistors.
키워드