Synthesis of Pipeline Structures with Variable Data Initiation Intervals

가변 데이터 입력 간격을 지원하는 파이프라인 구조의 합성

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.