Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 31A Issue 6
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- Pages.188-198
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- 1994
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- 1016-135X(pISSN)
Implementation of 2-D DCT/IDCT VLSI based on Fully Bit-Serial Architecture
완전 비트 순차 구조에 근거한 2차원 DCT/IDCT VLSI 구현
Abstract
The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.
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