Multi-level Logic Synthesis for Efficient Pseudoexhaustive Testing)

효율적 Pseudoexhaustive Testing을 위한 다단 논리합성

In this paper, we present a new multi-level logic synthesis method for producing the multi-level circuits which can be easily tested by the pseudoexhaustive testing techniques. The method consists of four stages. In the first stage, it generates the minimum variable supports for each output of a multiple-output function. In the second stage, it removes the minimum variable supports which if used to implement the outputs, lead to inefficient pseudoexhaustive test. In the third stage, it determines the minimum variable support and logic (uncomplementary or complementary logic) for each output. In the fourth stage, it performs the multi-level logic synthesis so that each output. In the fourth stage, it performs the multi-level logic synthesis so that each output has the minimum variable support and logic determined in the third stage. To evaluate the performance and quality of the proposed method, we have experimented on the 56 benchmark examples. The results show that for 56 examples, our method obtains better results than MIS in terms of testability. Moreover, the method produces better results for 19 examples and the same results for 12 examples compared with MIS in terms of literal count although it has been developed to improve the testability.