Abstract
Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.
