A scheduling algorithm for ASIC design

ASIC 설계를 위한 스케쥴링 알고리듬

In this paper, an intermediate representation HSFG(Hanyang Sequential Flow GRaph) and a new scheduling algorithm for the control-dominated ASIC design is presented. The HSFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. The scheduling algorithm minimizes the total operating time by reducing the number of the constraints as maximal as possible, searching a few paths among all the paths produced by conditional branches. The constraints are substitute by subgraphs, and then the number of subgraphs (that is the number kof the constraints) is minimized by using the inclusion and overlap relation among subgraphs. The proposed algorithm has achieved the better results than the previous ones on the benchmark data.