Efficient robust path delay fault test generation for combinational circuits using the testability measure

테스트 용이도를 이용한 조합회로의 효율적인 로보스트 경로 지연 고장 테스트 생성

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.