Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 300MHz CMOS phase-locked loop with improved pull-in process

루프인식 속도를 개선한 300MHz PLL의 설계 및 제작

  • 이덕민 (고려대학교 전자공학과 ASIC연구실) ;
  • 정민수 (고려대학교 전자공학과 ASIC연구실) ;
  • 김보은 (고려대학교 전자공학과 ASIC연구실) ;
  • 최동명 (삼성전자 마이크로사업부) ;
  • 김수원 (고려대학교 전자공학과 ASIC연구실)
  • Published : 1996.10.01
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Abstract

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

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