ETRI Journal

  • 제19권4호
  • /
  • Pages.317-325
  • /
  • 1997
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지

High-Speed Array Multipliers Based on On-the-Fly Conversion

  • Moh, Sang-Man (Section of Electronics and Telecommunicastions Research Institute) ;
  • Yoon, Suk-Han (Computer Technology Division, Electronics and Telecommunications Research Institute)
  • 발행 : 1997.12.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A new on-the-fly conversion algorithm is proposed, and high-speed array multipliers with the on-the-fly conversion are presented. The new on-the-fly conversion logic is used to speed up carry-propagate addition at the last stage of multiplication, and provides constant delay independent of the number of input bits. In this paper, the multiplication architecture and the on-the-fly conversion algorithm are presented and discussed in detail. The proposed architecture has multiplication time of (n +1)$t_{FA}$, Where n is the number of input bits and $t_{FA}$ is the delay of a full adder. According to our comparative performance evaluation, the proposed architecture has shorter delay and requires less area than the conventional array multiplier with on-the-fly conversion.

키워드

참고문헌

  1. IEEE Trans. on Computers v.22 no.12 A two's complement parallel array multiplication algorithm Baugh, C.R.;Wooley, B.A.
  2. IEEE Trans. on Electronic Computers A suggestion for a fast multiplier Wallace, C.S.
  3. Alta Frequenza v.19 Some schemes for parallel multipliers Dadda, L.
  4. Computer Design Development E. E. Swartzlander Jr.(ed.)
  5. Computer Arithmetic Algorithms Koren, I.
  6. Computer Arithmetic: Principles, Architecture, and Design Hwang, K.
  7. IEEE Trans. on Computers v.39 no.11 Fast multiplication without carry-propagate addition Ercegovac, M.D.;Lang, T.
  8. IEEE Trans. on Computers v.36 no.7 On-the-fly conversion of redundant into conventional representations Ercegova, M.D.;Lang, T.
  9. Proc. 11th IEEE Symp. on Computer Arithmetic n${\times}$n carry save multipliers without final addition Montuschi, P.;Ciminiera, L.
  10. IEEE Trans. on Computers v.23 no.12 A comment on A TWo's complement Parallel Array Multiplication Algorithm Blankenship, P.E.
  11. IEE Proceedings -Circuits, Devices and Systems v.142 no.1 Two's-complement fast serial-parallel multiplier Sunder, S.;El-Guibaly, F.;Antoniou, A.
  12. Principles of CMOS VLSI Design:A Systematic Perspective Weste, N.;Eshraghin, K.
  13. IEEE J. Solid State Circuits v.19 no.5 A CMOS floating-point multiplier Uya, M.;Kaneko, K.;Yasui, J.