A detailed FPGA routing by 2-D track assignment

이차원 트랙 할당에 의한 FPGA 상세 배선

  • 이정주 (삼성전자, 반도체 System LSI 본부, LSI2사업부 MICOM2팀) ;
  • 임종석 (서강대학교 전자계산학과)
  • Published : 1997.10.01

Abstract

In FPGAs, we may use the property of the routing architecture for their routing compared to the routing in the conventional layout style. Especially, the Xilinx XC4000 series FPGAs have very special routing architecture in which the routing problem is equivalent to the two dimensional track assignment problem. In this paper, we propose a new FPgA detailed routing method by developing a two dimensional trackassigment heuristic algorithm. The proposed routing mehtod accept a global routing result as an input and obtain a detailed routing such that the number of necessary wire segments in each connection block is minimized. For all benchmark circuits tested, our routing methd complete routing results. The number of used tracks are also similar to the results by thedirect routing methods.

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