2단 전류셀 매트릭스 구조를 지닌 저전압 고속 8비트 CMOS D/A 변환기

A los voltage high speed 8 bit CMOS digital-to-analog converter with two-stage current cell matrix architecture

  • 김지현 (LG 반도체㈜ 기술연구소, MIBU 설계3실) ;
  • 권용복 (정수기능대학 전자기술학과) ;
  • 윤광섭 (인하대학교 전자공학과)
  • 발행 : 1998.04.01

초록

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

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