Abstract
In this study, we focus on Ca contaminant which affects on the roughness Si substrate after thermal process. The initial Si substrates were contaminated intentionally by using a standard Ca solution. The contamination levels of Ca impurity were measured by TXRF and the chemical composition of that was analyzed by AES. Then we gre the thermal oxide to investigate the effect of Ca contaminants. The microroughness of the Si surface, the thermal oxide surface, and the surface after removing the thermal oxide were measured to examine the electrical characteristics. The initial substrates that were contaminated with the standard solution of Ca exhibited the contamination levels of 10\ulcorner~10\ulcorneratoms/$\textrm{cm}^2$ which was measured by TXRF. The Ca contaminants were detected by AES and exhibited the peaks of Ca, SI, C and O.After intentional contamination, the surface microroughness of this initial substrate was increased from $1.5\AA$ to 4$\AA$ as contamination levels became higher. The microroughness of the thermal oxide surfaces of both contaminated and bare Si substrates exhibits similar values. But the microroughness of the contaminated$ Si/SiO_2$ interface was increased as contamination increased. The thermal oxide of contaminated substrate exhibited the small minority carrier diffusion length, low breakdown voltage, and slightly high leakage current.
