NPSFs를 고려한 수정된 March 알고리즘

Modified March Algorithm Considering NPSFs

  • 김태형 (한양대학교 전자계산학과) ;
  • 윤수문 (한양대학교 전자계산학과) ;
  • 박성주 (한양대학교 전자계산학과)
  • Kim, Tae-Hyeong (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Yun, Su-Mun (Dept. of Computer Science & Engineering, Hanyang University) ;
  • Park, Seong-Ju (Dept. of Computer Science & Engineering, Hanyang University)
  • 발행 : 2000.04.01

초록

기존의 March 알고리즘으로는 내장된 메모리의 CMOS ADOFs(Address Decoder Open Faults)를 점검할 수 없다. 번지 생성 순서 및 데이터 생성을 달리 할 수 있다는 자유도(DOF: Degree of Freedom)에 근거한 수정된 March 알고리즘이 제안되었다. 본 논문에서는 번지생성기로 완전 CA(Cellular Automata)를, 데이터 생성기로 Rl-LFSRs(Randomly Inversed LFSRs)을 사용하여 수정된 March 알고리즘을 개선하였다. 본 알고리즘은 기존의 March 알고리즘에서 점검할 수 있었던 SAF, ADF, CF, TF, 및 CMOS ADOF의 완점점검은 물론, NPSFs(Neighborhood Pattern Sensitive Faults)도 추가로 점검할 수 있으며, 알고리즘의 복잡도는 O(n)을 유지한다.

The original March algorithms cannot detect CMOS ADOFs(Address Decoder Open Faults) which requires separate deterministic test patterns. Modified March algorithm using DOF(Degree of Freedom) was suggested to detect these faults in addition to conventional stuck faults. This paper augments the modified march test to further capture NPSFs(Neighborhood Pattern Sensitive Faults). Complete CA(Cellular Automata) is used for address generation and Rl-LFSRs(Randomly Inversed LFSRs) for data generation. A new modified March algorithm can detect SAF, CF, TF, CMOS ADOFs, and part of NPSFs. Time complexity of this algorithm is still O(n).

키워드

참고문헌

  1. Semiconductor Industry Association (SIA), The National Technology Readmap for Semiconductors, 1997
  2. R. W. Bassett et al., 'Boundary-scan design principles for efficient LSSD ASIC testing', IBM J. Res., Develop., vol. 34, no. 2/3, pp.339-353, 1990
  3. J. Otterstedt, D. Niggemeyer, & T.W. Williams, 'Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests,' ITC conf., Oct. 1998, pp.53-62 https://doi.org/10.1109/TEST.1998.743137
  4. D. Niggemeyer, M. Redeker, and J. Otterstedt, 'Intergration of Non-classical Faults in standard March Tests', Records of the IEEE Intl. WorkShop on Memory Technology, Design and Testing 1997, pp.27-32, San Jose, USA.
  5. M. Sachdev, 'Open Defects in CMOS RAM Address Decoders,' IEEE Design & Test of Comp., vol. 14, no. 2, pp.26-33, 1997 https://doi.org/10.1109/54.587738
  6. P. H. Bardell, 'Analysis of Celluar Automata Used as Pseudorandom Pattern Generators,' Proceedings of International Test Conference, 1990, pp. 762-768 https://doi.org/10.1109/TEST.1990.114093
  7. K. Cattell, S. Zhang, M. Serra, and J, C. Muzio, '2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application,' IEEE Trans. on Computers, vol. 48, Mar. 1999, pp. 285-295 https://doi.org/10.1109/12.754995
  8. A. J. Van de Goor, 'Testing Semiconductor Memories,' Theory and practice, John Wiley and sons; Chichester : UK, 1991
  9. E. J. McCluskey, S. Bozorgui-Nesbat, 'Design for Autonomous Test,' IEEE Trans. on Computers, vol. 30, no. 11, 1981
  10. 박종욱, 박경택, 조상욱, 박성주, '고밀도 메모리 테스트를 위한 개선된 램덤 BIST의 비교분석,' 한국정보과학회 가을 학술발표논문집, Vol. 24, NO. 2, 1997년 10월, pp.733-736