Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient Algorithm for Test Pattern Compaction using Independent Faults and Compatible Faults

독립고장과 양립 가능한 고장을 이용한 효율적인 테스트 패턴 압축 기법

  • Yun, Do-Hyeon (The Digital Media Research Center of LG Electronics) ;
  • Gang, Seong-Ho (Dept.of Mechanical Electronics Engineering, Yonsei University) ;
  • Min, Hyeong-Bok (Dept.of Electric Electronics Computer Engineering, Sungkyunkwan University)
  • 윤도현 (LG전자 Digital Media 연구소) ;
  • 강성호 (연세대학교 기계전자공학부) ;
  • 민형복 (성균관대학교 전기전자컴퓨터공학부)
  • Published : 2001.02.01
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Abstract

As combinational ATPG algorithms achieve effectively 100% fault coverage, reducing the length of test set without loosing its fault coverage becomes a challenging work. The new approach is based on the independent and the compatible relationships between faults. For more compact test set, the size of compatible fault set must be maximized, thus this algorithm generates fault-pattern pairs, and a fault-pattern pair tree structure using the independent and the compatible relationships between faults. With the fault-pattern pair tree structure, a compact test set effectively generated. The experimental results for ISCAS 85 and 89 benchmark circuits demonstrate the effectiveness of the proposed method.

조합회로에 대한 ATPG 알고리듬이 효율적으로 100%의 고장 검출율을 달성할 수 있게 되어 감에 따라서 고장 검출율을 그대로 유지한 상태에서 테스트 패턴을 줄이는 압축 기법의 중요성이 점차로 부각되고 있다. 본 논문에서 제시하는 알고리듬은 고장들간의 독립과 양립 관계에 기초해서, 압축된 테스트 패턴을 위해서는 양립할 수 있는 고장 집합의 크기를 크게 해야 하므로, 고장-패턴 쌍과 고장들간의 독립과 양립 관계를 이용해서 고장-패턴 쌍의 트리 구조를 생성하였다. 이 고장-패턴 트리를 바탕으로 해서 효율적으로 압축된 테스트 패턴을 생성할 수 있었고, ISCAS 85와 ISCAS 89 측정 기준 회로에 대한 결과로 제시된 알고리듬의 우수성을 검증하였다.

Keywords

References

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