Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient IEEE 1149.1 Boundary Scan Design for At-Speed Delay Testing

지연고장 점검을 위한 효율적인 IEEE 1149.1 바운다리스캔 설계

  • Kim, Tae-Hyung (Dept. of Computer Science & Engineering Hanyang University) ;
  • Park, Sung-Ju (Dept. of Computer Science & Engineering Hanyang University)
  • Published : 2001.10.01
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Abstract

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

현재의 IEEE 1149.1 바운다리스캔 표준안은 보드나 내장 코어의 연결선상의 지연고장은 점검 할 수 없다. 본 논문에서는 표준안에 위배기지 않게 TAP 제어기를 수정함으로 시스템 클럭 속도에서 지연고장을 점검 할 수 있는 기술을 개발하였다. 실험을 통해서 본 논문에서 제안한 방법이 기존의 방법보다 추가되는 면적이 적음을 보였다.

Keywords

References

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