Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Grouped Scan Chain Reordering Method for Wire Length Minimization

배선 길이 최소화를 위한 그룹화된 스캔 체인 재구성 방법

  • Published : 2002.08.01
Download PDF
⟨ Previous Next ⟩

Abstract

In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

대규모 VLSI 시스템을 설계하는 경우 스캔 플립플롭(이하 셀)을 채택한 스캔 테스트 방법을 사용하여 IC 칩의 테스트를 용이하게 한다. 이러한 경우 스캔체인에서의 스캔 셀들의 연결 순서는 물리적 설계과정인 셀들의 배치가 완료된 후 결정하여도 무방하다. 본 논문에서는 이러한 사실을 이용하여 스캔 셀간의 연결선의 길이가 작도록 이들의 순서를 조정하는 방법을 제안한다. 특히 본 논문에서 제안하는 방법은 스캔 셀들이 클럭 도메인별로 그룹화되어 있을 경우 이들의 순서를 결정하기 위하여 새롭게 제시되는 방법으로 기존의 재구성 방법에 비하여 약 13.6%의 배선길이를 절약할 수 있다. 또한, 스캔 셀 순서에 대한 여러 다양한 제약에 대하여 효율적으로 셀들의 순서를 재구성할 수 있다.

Keywords

References

  1. M. Abramovici, M. A. Breuer, & A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990
  2. R. Aroa & A. Albicki, 'Computer-Aided Scan Path Design For Self-Testing Chips,' Proc. of 29th Midwest Symp. on Circuits and Systems, pp. 301-304, Aug 1987
  3. K. D. Boese, A. B. Kahng., & S. Muddu. 'A New Adaptive Multi-Start Technique for Combinatorial Global Optimizations', Operations Research Letters, 16(2), Sept. 1994, pp. 101-113 https://doi.org/10.1016/0167-6377(94)90065-5
  4. M. R. Garey & D. S. Johnson, Computers and Intractability : A Guide to the Theory of NP-Completeness, W. H, Freeman, 1979
  5. M. Hirech, J. Beausang., & X, Gu. 'A New Approcah to Scan Chain Reordering Using Physical Design Information,' Proc. of ITC, 1998 https://doi.org/10.1109/TEST.1998.743173
  6. D. S. Johnson, 'Local Optimization and the Traveling Salesman Problem,' in Proc. of the 17th Int'l Colloquium on Automata Languages and Programming, pp. 446-460, July 1990
  7. S. Lin & B. W. Kernighan, 'An Effective Heuristic Algorithm for the Traveling Salesman Problem,' Operations Research 21, pp. 498-516, 1973 https://doi.org/10.1287/opre.21.2.498
  8. Freuer, M and C. Koo, 'Method for Rechaining shift Register Latches which Contain more than on Physical Book,' IBM Technical Disclosure Bulletin Vol. 25, No. 9, pp. 4818-4820, Fev. 1983
  9. E. L. Lawler., J. K. Lensta., A. H. G. Rinnoy Kan., & D.B. Shmoys, eds., The Traveling Salesman Problem, John Wiley & Sons, 1985
  10. S. Makar, 'A layout-Based Approach for Ordering Scan Chain Flip-Flops,' Proc. of ITC, 1998 https://doi.org/10.1109/TEST.1998.743172
  11. K. Nakaumra, et al. 'Scan path's Wire Length Minimization and Its Short Path Error Correction,' NEC Res. And Develop Vol. 38, No.1, pp. 22-27, Jan. 1997
  12. Barbagallo, S. et al. 'Scan Insertion Criteria for Low Design Impact,' Proc. of 14th VLSI Test Symposium, pp. 26-31, 1996
  13. J. Schmid & J. Knablein, 'Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs,' Proc. of 17th VLSI Test Symposium, 1999