Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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VLSI Design of a 2048 Point FFT/IFFT by Sequential Data Processing for Digital Audio Broadcasting System

순차적 데이터 처리방식을 이용한 디지틀 오디오 방송용 2048 Point FFT/IFFT의 VLSI 설계

  • Choe, Jun-Rim (School of Electronic & Electrical Engineering, Kyungpook National University)
  • 최준림 (경북대학교 전자전기공학부)
  • Published : 2002.05.01
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Abstract

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

본 논문에서는 순차적 입력 데이터 처리방식을 이용하여 2048 point FFT/IFFT를 단일 칩으로 구현하는 방법을 제안하고 검증하였다. 순차적으로 입력되는 2028개의 복소 데이터를 처리하기 위해서는 입력 데이터를 저장하는 버퍼가 필요하고 이 입력 버퍼로는 DRAM 회로를 이용한 지연 변환기 (delay commutator)를 사용하여 전체 칩 면적을 35% 이상 줄일 수 있었다. 전체 FFT/IFFT는 16 point FFT를 기본 블록으로 사용하며, radix-4 구조를 가지는 다섯 단계와 radix-2 구조를 가지는 하나의 단계로 이루어져 있다. 각 단계마다 연산을 수행하면서 증가되는 결과 S/N 비를 유지하면서 비트 라운딩을 하기 위해 convergent block floating point (CBFP) 알고리즘을 적용하여 digital audio broadcasting(DAB)을 위한 단일 칩 설계에 기여하였다.

Keywords

References

  1. Kenichi Taura, Masahiro T., Masuyuki T., Hiroaki K, Masayuki I., and Yoshinobu I., 'A digital audio broadcasting receiver,' IEEE transactions on Consumer Electronics, Vol. 42, No. 3, pp. 323-327, August 1996
  2. Louis Thibault and Mnh Thien Le, 'Performance evaluation of COFDM for digital audio broadcasting,' IEEE Transactions on broadcasting, Vol. 43, No. 1, pp. 64~75, March 1997 https://doi.org/10.1109/11.566826
  3. Kevin J. McGee, '64-point Fourier transform chip for video motion compensation using phase correlation,' IEEE J. Solid-state Circuits, Vol. 31, pp. 1751-1761, Nov. 1996 https://doi.org/10.1109/JSSC.1996.542320
  4. Bevan M Baas, 'A low-power, high performance 1024-point FFT processor,' IEEE Journal of Solid-state Circuits, Vol. 34, No. 3, pp. 380-387, Mar. 1999 https://doi.org/10.1109/4.748190
  5. F. rothan, C. joanblanq, and P. senn, 'A video delay line compiler,' Proc. ISCAS. New Orleans, L.A. pp. 65-68, May 1990 https://doi.org/10.1109/ISCAS.1990.111914
  6. John E. Whechel, John P. O'Mailey, William J. Rinard, and James F. McArthur, 'The systolic phase rotation FFT - a new algorithm and parallel processor architecture,' IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 1021-1024, April 1990 https://doi.org/10.1109/ICASSP.1990.116067
  7. John G. Proakis and Dimitris G. Manolakis, Digital signal processing, Prentice Hall. 1996
  8. Teress M Pytosh and Alberto M. Magnani, 'A new parallel 2-D FFT architecture,' IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 905-908. April 1990 https://doi.org/10.1109/ICASSP.1990.115993