Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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The Design of Speech Recognition Chip for a Small Vocabulary as a Word-level

소어휘 단어단위의 음성인식 칩 설계

  • 안점영 (동의대학교 전자공학과) ;
  • 최영식 (동의대학교 전자공학과)
  • Published : 2002.04.01
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Abstract

A speech recognition chip that can recognize a small vocabulary as a word-level has been designed. It is composed of EPD(Start and End-point detection) block, LPC block, DTW block and external memory interface block. It is made of 126,938 gates on 4x4mm2 area with a CMOS 0.35um TLM process. The speed of the chip varies from 5MHz to 60MHz because of its specific hardware designed for the purpose. It can compare 100,000 voices as a small vocabulary which has approximately 50∼60 frames at the clock of 5MHz and also up to 1,200,000 voices at the clock of 60MHz.

소어휘 단어단위의 음성을 인식할 수 있는 음성인식 칩을 설계하였다. 설계된 칩은 음성 신호의 시작과 끝점 검출 부분, LPC 켑스트럼 계수 추출 부분, DTW 실행 부분과 외부 메모리 인터페이스 부분으로 구성되어있다. CMOS 0.35um TLM 공정으로 설계된 이 칩은 4x4mm2의 면적에 126,938개의 게이트로 만들어져 있다. 그리고 전용 H/W의 동작 속도는 5MHz에서 60MHz까지 조정 가능하다. 5MHz 클록을 사용하는 경우, 50∼60 프레임 정도의 소어휘 단어 단위의 음성을 초당 100,000개까지 비교할 수 있는 능력이 있고, 60MHz의 클록을 사용하는 경우는 초당 1,200,000개의 단어를 비교할 수 있다.

Keywords

References

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