Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Logic Built-In Self Test Based on Clustered Pattern Generation

패턴 집단 생성 방식을 사용한 내장형 자체 테스트 기법

  • Kang, Yong-Suk (System IC Division, SIC R&D Center, LG Electronics Inc.) ;
  • Kim, Hyun-Don (Dept. of Electrical Eng., Yonsei Univ.) ;
  • Seo, Il-Suk (SOC Technology TE Group, System LSI Division Samsung Electronics co., LTD.) ;
  • Kang, Sung-Ho (Dept. of Electrical Eng., Yonsei Univ.)
  • 강용석 (LG 電子 電子技術院 시스템 IC 센터) ;
  • 김현돈 (延世大學校 電氣電子工學部) ;
  • 서일석 (三星電子 시스템 LSI 事業部 SOC 硏究所) ;
  • 강성호 (延世大學校 電氣電子工學部)
  • Published : 2002.07.01
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Abstract

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

본 논문에서는 패턴 집단 생성 방식을 사용한 새로운 내장형 자체 테스트를 위한 테스트 패턴 생성기를 제안하였다. 제안된 기술은 클럭당 테스트 환경에서 작은 하드웨어 크기를 가지면서 미리 계산된 결정 테스트 집합을 가진다. 테스트를 제어하기 위한 회로는 간단하여 자동적으로 합성된다. 새로운 패턴 생성기를 기존의 방법들과 비교한 결과를 ISCAS 벤치마크 회로를 가지고 검증하였다.

Keywords

References

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