ETRI Journal

  • 제25권5호
  • /
  • Pages.305-314
  • /
  • 2003
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
권호 표지

Soft IP Compiler for a Reed-Solomon Decoder

  • Park, Jong-Kang (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jong-Tae (School of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2003.01.15
  • 발행 : 2003.10.31
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초록

In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed-Solomon decoder with appropriate sub-architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.

키워드

참고문헌

  1. ETRI J. v.25 no.2 A Method and Tool for Identifying Domain Components Using Object Usage Information Lee, Woo-Jin;Kwon, Oh-Cheon;Kim, Min-Jung;Shin, Gyu-Sang
  2. Reuse Methodology Manual for System-on-a-Chip Designs Keating, M.;Bricaud, P.
  3. IEEE Des. & Test. Comput. v.18 no.3 A Survey of Digital Design Reuse Jacome, M.F.;Peixoto, H.P.
  4. Reed Solomon Decoder (D10337) Datasheet Tality Corp.
  5. RSDECD1 Reed-Solomon Decoder Mentor Invenra
  6. MC-XIL-RSDEC Reed-Solomon Decoder Memec design
  7. Reed-Solomon Decoder ISS
  8. The Microelectronics J. v.29 no.12 Design Automation of Reed-Solomon Codecs Using VHDL Smith, S.;Taylor, D.;Benaissa, M.
  9. Reed-Solomon Compiler User Guide Altera Corp.
  10. Reed-Solomon Decoder V.2.0, Xilinx LogiCore Xilinx Inc.
  11. VHDL Coding Guideline V.1.0 SIPAC
  12. High-Level Synthesis: Introduction to Chip and System Design Gajski, D.D.;Dutt, N.D.;Wu, W.C.;Lin, S.Y.
  13. IEEE Trans. Circuits Syst. Ⅱ: Analog and Digital Signal Processing v.47 no.11 Algorithm Based Low-Power/High-Speed Reed Solomon Decoder Design Raghupathy, A.;Liu, K.J.R.
  14. IEEE Trans. Comput. v.37 no.10 On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays Shao, H.M.;Reed, I.S.
  15. JKPS v.40 no.1 Efficient Recursive Cell Architecture for the Reed-Solomon Decoder Lee, D.H.;Kim, J.T.
  16. IEE Proc. of Computers and Digital Techniques v.138 no.5 VLSI Design of Inverse-Free Berlekamp-Massey Algorithm Reed, I.S.;Shih, M.T.;Truong, T.K.
  17. IEEE Trans. VLSI Syst. v.9 no.5 High-Speed Architectures for Reed-Solomon Decoders Sarwate, D.V.;Shanbhag, N.R.
  18. IEEE Trans. Commun. v.47 no.10 On Decoding of Both Errors and Erasures of a Reed-Solomon Code Using an Inverse-Free Berlekamp-Massey Algorithm Jeng, J.H.;Truong, T.K.
  19. Proc. of 4th Int'l Conf. on ASIC Parameterized IP Core Design Junchao, Z.;Weliang, C.;Shaojun, W.
  20. Proc. of EURO-DAC'95 How to Efficiently Build VHDL Testbenches Schutz, M.