Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design of Flag Based Wrapped Core Linking Module for Hierarchical SoC Test Access

계층적 SoC테스트 접근을 위한 플래그 기반 코아 연결 모듈의 설계

  • 송재훈 (한양대학교 전자컴퓨터공학부) ;
  • 박성주 (한양대학교 전자컴퓨터공학부) ;
  • 전창호 (한양대학교 전자컴퓨터공학부)
  • Published : 2003.01.01
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Abstract

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new flag based Wrapped Core Linking Module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

IEEE 1149.1 경계스캔 IP 코아로 설계된 시스템 칩(SoC)을 테스트하기 위하여 각 코아 간의 다양한 연결을 가능하게 하는 설계 기술이 IBM과 TI 등에서 제안되었다. 본 논문은 기존에 제안된 방식의 문제점을 분석하고 IEEE 1149.1 경계스캔 뿐만 아니라 IEEE P1500 래퍼 코아가 포함된 시스템 칩에서 사용할 수 있는 새로운 구조를 제안한다. 본 설계 기술은 최소한의 추가영역으로 코아의 설계변경 없이 IEEE표 1149.1 표준과 호환성을 유지하면서 확장성을 갖고 계층적으로 테스트 접근을 할 수 있다는 장점이 있다.

Keywords

References

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