대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

작은 룩업테이블을 가지는 새로운 파이프라인 나눗셈기

A New Pipelined Divider with a Small Lookup Table

  • 정웅 (연세대학교 전기전자공학과) ;
  • 박우찬 (연세대학교 컴퓨터과학과) ;
  • 곽승호 (연세대학교 전기전자공학과) ;
  • 양훈모 (연세대학교 전기전자공학과) ;
  • 정철호 (연세대학교 컴퓨터과학과) ;
  • 한탁돈 (연세대학교 컴퓨터과학과) ;
  • 이문기 (연세대학교 전기전자공학과)
  • Jeong, Woong (Dept. Electrical and Electronics, Yonsei University) ;
  • Park, Woo-Chan (Dept. Computer Science, Yonsei University) ;
  • Kwak, Sung-Ho (Dept. Electrical and Electronics, Yonsei University) ;
  • Yang, Hoon-Mo (Dept. Electrical and Electronics, Yonsei University) ;
  • Jeong, Cheol-Ho (Dept. Computer Science, Yonsei University) ;
  • Han, Tack-Don (Dept. Computer Science, Yonsei University) ;
  • Lee, Moon-Key (Dept. Electrical and Electronics, Yonsei University)
  • 발행 : 2003.09.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

기존의 나눗셈 연산기들은 대부분 반복적인 방식으로 연산을 수행하여 왔으나, 최근에는 파이프라인드 나눗셈 연산기에 대한 연구가 시도되고 있다. 현재 발표된 파이프라인 나눗셈 연산기는 큰 사이즈의 룩업테이블을 필요로 하기 때문에 면적을 크게 차지한다는 단점이 있다. 본 논문에서는 기존의 파이프라인드 나눗셈 연산기에 비해 룩업테이블을 크게 줄여, 비용에 효과적인 파이프라인 나눗셈 연산기를 제안한다. 제안하는 나눗셈 연산기는 단정밀도에서 3 사이클의 지연시간를 가지며, P. Hung의 방식에 비하여 약 30퍼센트 정도의 면적을 줄일 수 있다.

Generally, dividers have been designed to use iteration, but recently the research on the pipelined divider is underway. It is a difficult point in the known pipelined division unit that a large lookup table is required. In this paper, the cost-effective pipelined divider is proposed, that needs a lookup table smaller than that of the other pipelined divider. The latency of the proposed divider is 3 cycles. We obtain a 30% reduced area than that of P. Hung.

키워드

참고문헌

  1. S. F. Oberman and M. J. Flynn, 'Design Issues in Division and Other Floating Point Operations', IEEE Transactions on Computers, Vol. 46, No. 2, pp 154-161, Feb. 1997 https://doi.org/10.1109/12.565590
  2. P. Hung, H. Fahmy, O. Mencer and M. J. Flynn, 'Fast division algorithm with a small lookup table,' Conference Record of the Thirty Third Asilomar Conference on Signals, Systems and computers, Vol. 2, May pp 1465-1468, 1999 https://doi.org/10.1109/ACSSC.1999.831992
  3. A. A. Liddicoat and M. J. Flynn, 'Pipeline-able Division Unit,' Technical Report No. CSL-TR 00-809, Computer Systems Laboratory, Stanford University, pp 11-28, Sep. 2000
  4. I. Koren, Computer Aritymetic Algorithms, Prentice Hall, pp 153-161, 1993
  5. S. F. Oberman and M. J. Flynn, 'Division Algrotihms and Inplementations,' IEEE Transactions on Computers, Vol. 46, No. 8, pp 833-854, Aug. 1997 https://doi.org/10.1109/12.609274
  6. D. Wong and M. J. Flynn, 'Fast Division Using Accurate Quotient Apporximations to Reduce the Number of Iterations,' IEEE Transactions on Computers, Vol. 41, No. 8, pp 981-985, Aug. 1992 https://doi.org/10.1109/12.156541
  7. C. N. Lyu, D. Matula, 'Redundant Binary Booth Recoding,' Proceedings of IEEE Symposium on Computer Arithmetic, pp 50-57, Jul. 1995
  8. Samsung Electronics Co.Ltd., MDL110 0.25um 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products, 1999
  9. ANSI/IEEE standard 754-1985, IEEE Standard for Binary Floting-Point Arithmetic, 1985
  10. P.Soderquist and M.Leeser, 'Division and Square Root choosing the right implementations,' IEEE Micro, Vol. 17, pp 56-66, Jul./Aug. 1997 https://doi.org/10.1109/40.612224
  11. A. Kugler, 'The Setup for Triangle Rasterization,' 11th Eurographics Workshop on Computer Graphics Hardware, pp 49-58, Aug. 26 1996
  12. 11th Eurographics Workshop on Computer Graphics Hardware The Setup for Triangle Rasterization A.Kugler