한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제7권1호
  • /
  • Pages.122-128
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  • 2003
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
권호 표지

A Design of 16${\times}$16-bit Redundant Binary MAC Using 0.25 ${\mu}{\textrm}{m}$ CMOS Technology

  • Kim, Tae-Min (Dept.of Electronics Engineering, Kumoh National Institute of Technology) ;
  • Shin, Gun-Soon (Dept. of Information Communication, Kumi Collage)
  • 발행 : 2003.03.01
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초록

In this paper, a 16${\times}$16-bit Multiplier and Accumulator (MAC) is designed using a Redundant Binary Adder (RBA) circuit so that it can make a fast addition of the Redundant Binary Partial Products (RB_PP's) by using Wallace-tree structure. Because a RBA adds two RB numbers, it acts as a 4-2 compressor, which reduces four inputs to two output signals. We propose a method to convert the Redundant Binary (RB) representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient RB number to binary number converter can be designed with new conversion method.

키워드

참고문헌

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